1. Field of the Invention
The present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), memory and computer peripherals together, and more particularly, in utilizing a registered peripheral component interconnect bus, logic circuits therefor and signal protocols thereof.
2. Description of the Related Technology
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be used as stand-alone workstations (high end individual personal computers) or linked together in a network by a xe2x80x9cnetwork serverxe2x80x9d which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail (xe2x80x9ce-mailxe2x80x9d), document databases, video teleconferencing, whiteboarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks (xe2x80x9cLANxe2x80x9d) and wide area networks (xe2x80x9cWANxe2x80x9d).
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the xe2x80x9cPENTIUMxe2x80x9d and xe2x80x9cPENTIUM PROxe2x80x9d (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Compaq Computer Corporation, Cyrix, IBM and Motorola. These sophisticated microprocessors have, in turn, made possible running more complex application programs that require higher speed data transfer rates between the central processor(s), main system memory and the computer peripherals.
Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit (xe2x80x9cCPUxe2x80x9d). The peripheral devices"" data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the xe2x80x9cPeripheral Component Interconnectxe2x80x9d or xe2x80x9cPCI.xe2x80x9d A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; the disclosures of which are hereby incorporated by reference. These PCI specifications are available from the PCI Special Interest Group, 2575 NE Kathryn Street, Suite 17, Hillsboro, Oreg. 97124.
The PCI version 2.1 Specification allows for a 33 MHz or 66 MHz, 32 bit PCI bus; and a 33 MHz or 66 MHz, 64 bit PCI bus. The 33 MHz, 32 bit PCI is capable of up to 133 megabytes per second (xe2x80x9cMB/sxe2x80x9d) peak and 50 MB/s typical; and the 66 MHz, 32 bit PCI bus, as well as the 33 MHz 64 bit PCI bus, are capable of up to 266 MB/s peak. The PCI version 2.1 Specification, however, only allows two PCI device cards (two PCI connectors) on a 66 MHz PCI bus because of timing constraints such as clock skew, propagation delay, input setup time and valid output delay. Typically, the 66 MHz PCI version 2.1 Specification requires the sourcing agent to use a late-arriving signal with a setup time of only 3 nanoseconds (xe2x80x9cnsxe2x80x9d) to determine whether to keep the same data on the bus or advance to the next data, with a 6 ns maximum output delay. Current state of the art Application Specific Integrated Circuits (xe2x80x9cASICxe2x80x9d) using 0.5 micron technology have difficulty meeting the aforementioned timing requirements. Even using the newer and more expensive 0.35 micron ASIC technology may be marginal in achieving the timing requirements for the 66 MHz PCI bus.
Since the introduction of the 66 MHz timing parameters of the PCI Specification in 1994, bandwidth requirements of peripheral devices have steadily grown. Devices are beginning to appear on the market that support either a 64-bit bus, 66 MHz clock frequency or both, with peak bandwidth capabilities up to 533 Mbytes/s. Because faster I/O technologies such as Gigabit Ethernet and Fiberchannel are on the horizon, faster system-interconnect buses will be required in the future.
When an industry outgrows a widely accepted standard, that industry must decide whether to replace the standard or to enhance it. Since the release of the first PCI Specification in 1992, the PCI bus has become ubiquitous in the consumer, workstation, and server markets. Its success has been so great that other markets such as industrial controls, telecommunications, and high-reliability systems have leveraged the specification and the wide availability of devices into specialty applications. Clearly, the preferred approach to moving beyond today""s PCI Local Bus Specification is to enhance it.
What is needed is an apparatus, method, and system for a personal computer that provides increased data throughput between the personal computer system central processing unit(s), memory and peripherals that can operate at speeds significantly higher than today""s PCI Specification allows. In addition, the present invention shall still be compatible with and be able to operate at conventional PCI speeds and modes when installed in conventional computer systems or when interfacing with a conventional PCI device(s) or card(s).
The present invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing in a computer system a registered peripheral component interconnect bus, logic circuits therefor and signal protocols thereof.
The present invention includes a preferred embodiment having revised read and write transaction protocols that add an attribute phase immediately after the standard PCI address phase to the transaction. The additional phase enables the inclusion of an extended set of commands. The inclusion of an attribute phase with an extended command set allows for maximum backward compatibility while still allowing for faster transfer rates.
A first alternate embodiment of the present invention adds a side-band address port to the PCI-X bus to enable devices to enqueue multiple requests onto the PCI-X bus. By using the side-band address port, addresses can be separated (i.e., utilize separate pins) from the data pins.
A second alternate embodiment of the present invention utilizes a multi-cast bus consisting of one command/control signal line and one or more data lines for multiplexed command/data/request signals. The multicast bus of the second embodiment enables a second PCI-X devices to receive data targeted for a first PCI-X device without having to send the same data twice over the bus. Thus, the second embodiment facilitates redundant arrays of input/output devices (RAID).
A third alternate embodiment capitalizes on the byte count transaction protocol of the PCI-X specification. By using the byte-count information, the memory controller of this embodiment can schedule the next subsequent memory transactions without waiting for the next multiple PCI-X read requests. The memory controller can issue several internal memory requests to several memory ports, if available, without waiting for the next ADS# or PCI-X read transactions. Because these addresses are sequential, the memory controller can take advantage of xe2x80x9cpage hitxe2x80x9d cycles, and/or pipeline the memory cycles to further reduce the memory latencies.
A fourth alternate embodiment enables PCI-X devices to perform pipelined bus transactions. This is accomplished by interleaving the pipelined transaction with PCI-X protocol transactions on the PCI-X bus. The pipelined transactions, however, are limited only to memory read and write bus operations targeted at the main memory.
Additional embodiments will be clear to those skilled in the art upon reference to the detailed description and accompanying drawings.